With advancements in IC scaling with smaller technology nodes, defect detection and overlay metrology are becoming more challenging. Standard optical overlay (OVL) structures are large (e.g. in micrometers) and require placement in large spaces of frame or in reserved blank spaces within the chip/die area. An alternative to using the standard optical method may be to use a critical dimension scanning electron microscope (CDSEM). However, use of the CDSEM requires compatible dimensions and appearance of the structures on a reference layer that can be exposed and dimensions of the underlying layer can be assessed. Such evaluations are particularly problematic for interconnects due to limited visibility of buried layers.
Therefore, a need exists for methodology enabling in-die overlay reticle measurement and the resulting devices.